library verilog;
use verilog.vl_types.all;
entity mod_arbiter_imp_gen is
    generic(
        ch_num          : integer := 8
    );
    port(
        clk             : in     vl_logic;
        addr            : out    vl_logic_vector(31 downto 0);
        wre             : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of ch_num : constant is 1;
end mod_arbiter_imp_gen;
